The present invention relates to FinFET structures and, more particularly, relates to the formation of an implanted layer adjacent to the gate to seal the gate prior to a subsequent epitaxial silicon step in which raised source/drains are formed in the FinFET structure.
FinFET devices and FinFET structures are nonplanar devices and structures typically built on a semiconductor on insulator (SOI) substrate. The FinFET devices may comprise a vertical semiconductor fin, rather than a planar semiconductor surface, having a single or double gate wrapped around the fin. In an effort to provide for continued scaling of semiconductor structures to continuously smaller dimensions while maintaining or enhancing semiconductor device performance, the design and fabrication of semiconductor fin devices and semiconductor fin structures has evolved within the semiconductor fabrication art.